Reference is now made to FIG. 1 which depicts a general block diagram of a successive approximation analog to digital converter 10. The successive approximation analog to digital converter 10 comprises a sample and hold circuit 12, a comparator 14, a successive approximation register (SAR) 16, and a digital to analog converter (DAC) 18. The sample and hold circuit 12 acquires an analog input voltage V. The comparator 14 compares analog input voltage Vin to the analog output voltage of the DAC 18 and outputs a digital signal to the SAR 16 representative of the comparison. The SAR 16 supplies an approximate digital representation of analog input voltage Vin to the DAC 18 and the DAC 18 supplies the comparator 14 with the analog voltage equivalent of the digital output of the SAR 16 for comparison with analog input voltage Vin. The SAR 16 is initialized so that the most significant bit (DMSB) is equal to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code (VREF/2) into the comparator 14 for comparison with the sampled input voltage Vin held by the output of sample and hold circuit 12. If the analog input voltage Vin exceeds VREF the comparator 14 signals the SAR 16 to set DMSB to 0 otherwise, DMSB remains a 1. Next DMSB-1 is set to 1 and the same test is performed by comparator 14. This cycle is repeated with the next bit until every bit in the SAR 16 has been tested down to D0. The resulting output from the SAR 16 at the end of the conversion (EOB) is the digital approximation of the sampled input voltage Vin which is finally output by the DAC 18.
Reference is now made to FIG. 2 which depicts a differential input, switched capacitor/resistor DAC 18 for use with a successive approximation analog to digital converter. The switched capacitor DAC 18 comprises an array 20 of individually switched, binary-weighted capacitors 1C-16C in combination with resistor divider array 21 having resistors R1-R128. It is to be understood that the DAC 18 could be implemented entirely with switched capacitors without the resistor divider array 21 without departing from the scope of the present invention. The digitization cycle starts by sampling the differential analog input (AINM AINP) and resetting the sense nodes of comparator 14 to half the analog supply (AVDD/2) by switching on comparator input reset switches 22a and 22b. A Person Having Ordinary Skill in the Art (PHOSITA) will readily recognize that only one switch is used for single-ended applications. The reset switches 22a and 22b are turned off during the approximation cycles (12 clock cycles for 12 bit ADC). During this time however, as explained in more detail herein below, switches 22a and 22b are injecting undesirable, voltage dependent leakage current into the input sense nodes of comparator 14 which accumulate enough charge to cause significant linearity errors. The problem is particularly acute at strong CMOS model corners and elevated temperatures when using deep submicron processes.
Reference is now made to FIG. 3 that depicts a typical switch 22 used for reset switches 22a and 22b. Switch 22 comprises a pMOS transistor and nMOS transistor coupled in parallel with their respective source and drain terminals coupled together. The gates of the pMOS and nMOS transistors are controlled in a complementary manner so that both transistors are either on or off When the voltage on the gate terminal is a logical 1 both the pMOS and nMOS transistor conduct and pass the signal between the analog supply (AVDD/2) and an input sense node on comparator 14. When the voltage on the gate terminal is a logical 0, both transistors are turned off forcing a high-impedance condition. In such an arrangement, the pMOS transistor in the switch 22 typically leaks current through the NWELL bulk node. Accordingly, the leakage current degrades the linearity of the analog to digital converter during successive approximation cycles.